(1) Fields of the Invention
The present invention relates generally to fabrication of semiconductor devices and more particularly to a anisotropic etch process for a multilayer silicon self aligned gate (SAG) for metal oxide semiconductor field effect transistor (MOSFET) where the etching process of the inorganic buried anti-reflective coating (Barc) layer over silicon results in repeatable etch time end points for the removal of the Barc.
(2) Description of Prior Art
The stacked gate multilayer structure of the current reduced size FET's has become common. As device size is reduced the etching process required to create the correct topography has become more critical.
Dry etching is a process in which a gas or plasma containing at least one reactive species which is energized by a radio frequency when placed in contact with a structure to be etched. This causes a reaction at the surface of the material to be etched wherein the reactant material is removed in the form of a gas. The status of the etch process as it progresses through the various materials of a multilayer gate element is monitored by an optical detector which monitors the optical emission from the plasma. The process begins with an application of a masking material such as photoresist (PR) on a multilayer semiconductor structure. The masking material patterns an area on the structure from the etch process, for instance, to create a field effect transistor (FET) gate structure. The structure or wafer is placed in a plasma reactor, that is, etcher, and etching is initiated. Two common problems with this dry etch process is the undercutting of the polysilicon gate layer, and the etch consistency of the process as it etches through the various layers of a composite layer gate structure. Another potentially serious environmental problem is the use of a reactant such as carbon tetrachloride (CCl.sub.4), which can be potentially harmful to the environment as an ozone destroying chemical.
A common silicon/polysilicon etch process is based on fluorine. When mixtures such as carbon tetrafluoride (CF.sub.4) and oxygen (O.sub.2) are disassociated in an electrical discharge, fluorine atoms are liberated and volatilize the silicon as silicon tetrafluoride (SiF.sub.4), Nevertheless, these processes are isotropic, that is they etch in all directions, laterally as well as vertically. with the same rate. Anisotropic or vertical only etches are not produced when fluorine is the sole enchant.
For vertical (anisotropic) etches of silicon or polysilicon, the uses of gas mixtures such as CF.sub.4 and chlorine (Cl.sub.2) are used. The recombinants suppress etching in the lateral, that is in the horizontal direction, by recombining with the Cl.sub.2 atoms which have adsorbed on the etched polysilicon walls. Etching continues in the vertical direction perpendicular to the wafer surface because bombardment from the plasma suppresses the recombination mechanism. This sidewall passivation effect is described by S. M. Sze in his book VLSI Technology, Second Edition, McGraw-Hill International Editions, New York, N.Y. 1988, page 200.
Furthermore, the selectivity of etch between polysilicon and gate oxide (poly:oxide selectivity) must be as high as possible to minimize oxide loss. In addition to an etch step, most conventional processes include an overetch step. Overetching is necessary in order to insure no unwanted residues are left on the wafer or device structure after etching. If etching was stopped at the "end point" as determined by the optical emission from the plasma, only parts of the wafer would be completely etched while other parts would still be covered by some remaining polysilicon or buried or bottom anti reflective coating layer (Barc) material. The Barc layer is used to both help planarize the surface and to reduce light scattering from the semiconductor surface into the resist which helps in the definition of small images. The after etch residue is due to the non uniformity of both the initial polysilicon or Barc film thickness and the etch rate. Many of the overetch process gases contain chloride such as CCl.sub.4 which can be harmful to the environment as an ozone destroying chemical as previously noted.
FIG. 2 illustrates an acceptable polysilicon etch profile. Substrate 10 is covered by a gate oxide 12, polysilicon gate 14, silicide 16, another poly layer 18 covered by a "buried" or bottom antireflective coating layer (Barc) 20 and photoresist 22. The polysilicon gate sidewall is vertical; it is not undercut 24 as shown in FIG. 3, nor does it have a "foot" 26 at the base of the poly gate as shown in FIG. 4. Both undercutting and foot formation result from complicated etch (isotropic and anisotropic) and deposition reactions. For example, the undercutting can result from enhanced isotropic etching near the bottom of the structure. Foot formation can be caused by redeposition which can have a higher rate at the bottom of a small etching region. It is common industry practice to eliminate "foot" formation with polysilicon gates by performing an overetch step after the main etch step. The overetch consumes the foot as well as any residual polysilicon on the oxide surface. In order to prevent undercutting, it is necessary to form a deposit on the polysilicon sidewall to protect the side wall from ions in the plasma which can laterally etch the sidewall. A process is desirable that produces the proper gate profile without undercutting and other anomalies such as a "foot", which uses chemical gases which are not harmful to the environment or reduce the quantities used of potentially harmful gases, and is reproducible over many different wafers during a manufacturing process.
The following terms and abbreviations are or may be used herein; Polysilicon (poly); Carbon (C); Carbon Tetrachloride (CCl.sub.4); Carbon Tetrafluoride (CF.sub.4); Chlorine (Cl.sub.2); Fluorine (F); field effect transistor (FET); Helium (He); Hydrogen (H.sub.2); milli Torr (mT); standard cubic centimeters per minute (sccm); Angstroms (.ANG.); microns (.mu.m); watts (w); etch rate (ER); seconds (sec); ratio of one element (X) to another (Y) (X:Y), bottom (or buried) anti-reflective coating (Barc), Centigrade (.degree.C.), self aligned gate (SAG).
U.S. Pat. No. 5,804,088 issued to McKee and U.S. Pat. No. 5,858,621 issued to Yu et al show methods for etching multilayer FET gate structures containing anti-reflective coating layer(s), U.S. Pat. No. 5,885,902 issued to Blasingame et al. shows for etching a multilayer gate structure containing an arc layer with different reactant gases. U.S. Pat. No. 5,188,980 issued to Lai describes an inert gas purge enchant process for a multilayer gate structure. U.S. Pat. No. 5,453,156 issued to Cher et al. describes a multilayer gate element dry anisotropic etch eliminating CCl.sub.4 from the enchant chemistry.